Alif Semiconductor /AE512F80F5582AS_CM55_HP_View /SDMMC /SDMMC_PRESET_SDR50_R

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Interpret as SDMMC_PRESET_SDR50_R

CLK_GEN_SEL_VAL=Val_0x0, DRV_SEL_VAL=Val_0x0

Description

Register with Preset Value for SDR50

Fields

FREQ_SEL_VAL	SD_CLK Frequency Select Value. 10-bit preset value to be set in the SDMMC_CLK_CTRL_R[FREQ_SEL] bit field described by a Host System.
CLK_GEN_SEL_VAL	Clock Generator Select Value. This bit is effective when the Host Controller supports programmable clock generator. 0 (Val_0x0): Host Controller Ver2.0 compatible clock generator 1 (Val_0x1): Programmable clock generator
DRV_SEL_VAL	Driver Strength Select Value. These bits indicate Driver strength value supported for SDR50 bus speed mode. These bits are meaningless for 3.3 V signaling. 0 (Val_0x0): Driver Type B is selected 1 (Val_0x1): Driver Type A is selected 2 (Val_0x2): Driver Type C is selected 3 (Val_0x3): Driver Type D is selected

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